1. Field of the Invention
The present invention relates to a semiconductor protection circuit and a semiconductor protection device, more specifically to those designed to protect a main semiconductor device from a surge voltage applied to an input/output terminal for a high-frequency signal, from outside.
2. Description of the Related Art
Semiconductor protection circuits generally used are shown in FIGS. 1, 2 and 3.
In the circuit shown in FIG. 1, between an internal circuit 100 and its input/output terminal 101, a power source Vcc (maximum potential) is connected via a PN diode 102, and so is a minimum potential (ground) via a Schottkey diode. A cathode of the PN diode 102 is connected to the power source vcc, and an anode is connected to the input/output terminal 101. Further, a cathode of the Schottkey diode 103 is connected to the input/output terminal 101, and an anode is connected to the minimum potential.
According to the circuit shown in FIG. 1, in the case where a positive surge potential higher than Vcc (maximum potential) is applied to the input/output terminal 101, the PN diode 102 is rendered conductive, thereby protecting the internal circuit 100. In the case where a negative surge potential lower than the minimum potential is applied to the input/output terminal 101, the Schottkey diode 103 is rendered conductive, thereby protecting the internal circuit 100.
In the circuit shown in FIG. 2, between an internal circuit 100 and its input/output terminal 101, a power source Vcc (maximum potential) is connected via a PMOS transistor 104, and so is a minimum potential (ground) via an NMOS transistor 105. Drains of both MOS transistors 104 and 105 are connected to the input/output terminal 101, and gates and sources are connected to the power source Vcc or the minimum potential.
According to the circuit shown in FIG. 2, in the case where a positive surge potential is applied to the input/output terminal 101, the PMOS transistor 104 is rendered conductive, thereby protecting the internal circuit. In the case where a negative surge potential is applied to the input/output terminal 101, the NMOS transistor 105 is rendered conductive, thereby protecting the internal circuit 100.
In the circuit shown in FIG. 3, a bipolar transistor is provided in order to help a MOS transistor having a low current driving property. Between an internal circuit 100 and its input/output terminal 101, a power source Vcc (maximum potential) is connected via an NPN bipolar transistor 106, and so is a minimum potential (ground) via a Schottkey diode 103. An emitter of the bipolar transistor 106 is connected to the power source Vcc, and a collector is connected to the input/output terminal. A cathode of the Schottkey diode 103 is connected to the input/output terminal 101, and an anode is connected to the minimum potential. Further, a source of an NMOS transistor 107 is connected to a base of the bipolar transistor 106. A gate and a drain of the MOS transistor 107 are connected to the input/output terminal 101.
According to the circuit shown in FIG. 3, in the case where a positive surge potential is applied to the input/output terminal 101, the NPN bipolar transistor 106 is rendered conductive, thereby protecting the internal circuit. In the case where a negative surge potential is applied to the input/output terminal 101, the Schottkey diode 103 is rendered conductive, thereby protecting the internal circuit 100.
Next, the structure of a conventional semiconductor protection device will be described with reference to FIG. 4. FIG. 4 is a cross sectional view of a structure in which the protection circuit shown in FIG. 3 is realized on a semiconductor substrate, including the NPN bipolar transistor 106 and the NMOS transistor 107.
N-type well layers 114a, 114b and 114c are formed in the surface region of a P-type semiconductor substrate, and an oxide film 115 is selectively formed on the substrate 111 such as to surround these layers. A thin oxide film 117 is formed on the N-type well layers 114a, 114b and 114c so as to protect the surface of the substrate 111.
A polysilicon gate electrode 118 is provided between the N-type well layers 114a and 114b, which serve as the drain and source of the NMOS transistor 107, on the oxide film. High-concentration N-type layers 121 and 120 are formed in the surface regions of the N-type well layers 114a and 114b. Further, a P-type base layer 125 is formed in the surface region of the N-type well layer 114c which serves as the collector of the NPN bipolar transistor 106 and an N-type emitter layer 126 is formed in the surface region of the base layer.
An SiO.sub.2 insulation film 122 is deposited on the substrate 111 by the CVD. Contact holes are formed in the insulation film 122, and electrodes 123 are provided in these holes.
The conventional protection circuits share a common problem in which a large parasitic capacitance of the protection circuit is assigned to the input/output terminal, where high-frequency signals pass by, thus reducing the signal charge. Therefore, in order to achieve a high frequency characteristic, a protection circuit cannot be provided. As a result, the reliability as regards static breakage must be inevitably deteriorated. Apart from this, the conventional circuits entail the drawbacks described below.
FIG. 5 illustrates an example in which two protection circuits such as shown in FIG. 1 are provided on boards B1 and B2, which are connected to each other via a connection cord C. In this case, in the case where the power voltage of the circuit of the board B1 is maintained at the regular operation level while the power of the circuit on the board B2 is turned off, thus reducing the potential at the position L2 to the GND level, the PN diode 102 of the board B2 is turned on since the output voltage of the board B1 (the potential at the position L1 in the figure) is at a high level. Thus, an undesired current flows from the position L1 to the position L2, causing a loss of the signal charge applied to the input/output terminal.
Further, in the case where a bipolar transistor and an MOS transistor are provided as shown in FIG. 4, in order to avoid the damage to circuit due to the concentration of the breakdown current, the area occupied by the entire protection device is increased, raising another drawback in terms of high degree of integration.